CSTRT=0, SSGTRGBR=0, SSELCD=0, SSCAFBH=0, SSCBFAL=0, SSGTRGDF=0, SSGTRGDR=0, SSELCE=0, SSELCA=0, SSCBRAH=0, SSCBFAH=0, SSCBRAL=0, SSGTRGCF=0, SSGTRGCR=0, SSGTRGBF=0, SSGTRGAF=0, SSELCG=0, SSELCF=0, SSELCC=0, SSCAFBL=0, SSCARBL=0, SSCARBH=0, SSELCH=0, SSGTRGAR=0, SSELCB=0
General PWM Timer Start Source Select Register
| SSGTRGAR | GTETRGA Pin Rising Input Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTETRGA input 1 (1): Enable counter start on the rising edge of GTETRGA input. |
| SSGTRGAF | GTETRGA Pin Falling Input Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTETRGA input 1 (1): Enable counter start on the falling edge of GTETRGA input |
| SSGTRGBR | GTETRGB Pin Rising Input Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTETRGB input 1 (1): Enable counter start on the rising edge of GTETRGB input. |
| SSGTRGBF | GTETRGB Pin Falling Input Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTETRGB input 1 (1): Enable counter start on the falling edge of GTETRGB input |
| SSGTRGCR | GTETRGC Pin Rising Input Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTETRGC input 1 (1): Enable counter start on the rising edge of GTETRGC input |
| SSGTRGCF | GTETRGC Pin Falling Input Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTETRGC input 1 (1): Enable counter start on the falling edge of GTETRGC input |
| SSGTRGDR | GTETRGD Pin Rising Input Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTETRGD input 1 (1): Enable counter start on the rising edge of GTETRGD input |
| SSGTRGDF | GTETRGD Pin Falling Input Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTETRGD input 1 (1): Enable counter start on the falling edge of GTETRGD input. |
| SSCARBL | GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 0 1 (1): Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 0. |
| SSCARBH | GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTIOCA input when GTIOCB input is 1 1 (1): Enable counter start on the rising edge of GTIOCA input when GTIOCB input is 1 |
| SSCAFBL | GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 0 1 (1): Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 0. |
| SSCAFBH | GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTIOCA input when GTIOCB input is 1 1 (1): Enable counter start on the falling edge of GTIOCA input when GTIOCB input is 1. |
| SSCBRAL | GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 0 1 (1): Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 0. |
| SSCBRAH | GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable 0 (0): Disable counter start on the rising edge of GTIOCB input when GTIOCA input is 1 1 (1): Enable counter start on the rising edge of GTIOCB input when GTIOCA input is 1. |
| SSCBFAL | GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 0 1 (1): Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 0. |
| SSCBFAH | GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable 0 (0): Disable counter start on the falling edge of GTIOCB input when GTIOCA input is 1 1 (1): Enable counter start on the falling edge of GTIOCB input when GTIOCA input is 1. |
| SSELCA | ELC_GPTA Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTA input 1 (1): Enable counter start on ELC_GPTA input. |
| SSELCB | ELC_GPTB Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTB input 1 (1): Enable counter start on ELC_GPTB input. |
| SSELCC | ELC_GPTC Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTC input 1 (1): Enable counter start on ELC_GPTC input. |
| SSELCD | ELC_GPTD Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTD input 1 (1): Enable counter start on ELC_GPTD input. |
| SSELCE | ELC_GPTE Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTE input 1 (1): Enable counter start on ELC_GPTE input |
| SSELCF | ELC_GPTF Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTF input 1 (1): Enable counter start on ELC_GPTF input |
| SSELCG | ELC_GPTG Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTG input 1 (1): Enable counter start on ELC_GPTG input. |
| SSELCH | ELC_GPTH Event Source Counter Start Enable 0 (0): Disable counter start on ELC_GPTH input 1 (1): Enable counter start on ELC_GPTH input. |
| Reserved | These bits are read as 0000000. The write value should be 0000000. |
| CSTRT | Software Source Counter Start Enable 0 (0): Disable counter start by the GTSTR register 1 (1): Enable counter start by the GTSTR register |